a) Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a metal wiring at the peripheral area of the chip.
b) Description of the Related Art
An example of a conventional semiconductor device will be described with reference to FIGS. 10 and 11.
FIG. 10 is a plan view showing the structure of a corner area of a semiconductor device (semiconductor chip). As shown in FIG. 10, a silicon chip 1 has a wide metal wiring 2 formed on the upper surface of the chip 1 at its peripheral area. The metal wiring 2 is made of aluminum or the like, and is bent at the corner by about 90 degrees. Such a wide metal wiring 2 is generally used as a power source line or a common (ground) line. FIG. 11 is a cross sectional view taken along line A--A' of FIG. 10. As shown in FIG. 11, on the upper surface of a silicon substrate 3 there are formed silicon oxide films 4 and 5, and the above-described metal wiring 2 being formed on the silicon oxide film 5. A passivation film 8 formed of polyimide, silicon nitride or the like covers the metal wiring 2 and oxide film 5.
Thermal stresses are applied from sealing resin to underlying layers of a semiconductor device. Thermal stresses are generated depending upon external environments, heat dissipation by power-on, or the like. Specifically, stresses are generated in accordance with differences of thermal expansion and contraction characteristics among a semiconductor substrate, oxide films, wiring layers, sealing resin and the like. Stresses are applied in the directions indicated by arrows in FIGS. 10 and 11, and concentrated on a corner area. With larger stresses at the corner area, the metal wiring 2 slides toward the inside of the chip in some cases. Such a phenomenon is conspicuous at the corner area, although it is not limited only at the corner area. Cracks may occur in a passivation film depending upon the magnitude of stress.
To solve the above problems, the following approaches have been made conventionally:
(a) forming no metal wiring at a chip corner area as shown in FIG. 12A; PA1 (b) forming narrow parallel metal wirings 2a, 2b, 2c in place of a wide metal wiring to disperse and reduce stresses as shown in FIG. 12B; and PA1 (c) forming some narrow slits 9a, 9b in a wide metal wiring 2 in the longitudinal direction thereof to disperse and reduce stresses as shown in FIG. 12C.
However, the approach (a) requires an empty space at the chip corner, lowering a usage factor of the chip surface. The approach (b) has some advantageous effect and is presently used, but it is not satisfactory in that metal wiring slide cannot be completely eliminated. The approach (c) generates a local current concentration, degrading the performance of devices.